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1 ISL36411 quad lane extender ISL36411 the ISL36411 is a settable quad receive-side equalizer with extended functionality for advanced protocols operating with line rates up to 11.1gbps such as infiniband (qdr) and 40g ethernet (40gbase-cr4/ sr4). the ISL36411 compensates for the frequency dependent attenuation of copper twin-axial cables, extending the signal reach up to at least 10m on 28awg cable. the small form factor, highly-integrated quad design is ideal for high-density data transmission applications including active copper cable assemblies. the four equalizing filters within the ISL36411 can each be set to provide optimal signal fidelity for a given media and length. the compensation level for the filters is set by two external control pins. operating on a single 1.2v power supply, the ISL36411 enables per channel throughputs of 10gbps to 11.1gbps while supporting lower data ra tes including 8.5, 6.25, 5, 4.25, 3.125, and 2.5gbps. the ISL36411 uses current mode logic (cml) inputs/outputs and is packaged in a 4mmx7mm 46-lead qfn. individual lane los support is included for module applications. features ? supports four channels with data rates up to 11.1gbps ? low power (~110mw per channel) ? low latency (<500ps) ? four equalizers in 4mmx7mm qfn package for straight route-through architecture and simplified routing ? equalizer boost is pin selectable ? pin selectable equalizer boosts ? supports 64b/66b encoded data - long run lengths ? line silence preservation & individual lane los support ? 1.2v power supply ? los support applications ? qsfp active copper cable modules ? infiniband qdr ? 40g ethernet (40gbase-cr4/sr4) ? 100g ethernet (100gbase-cr10/sr10) ? high-speed active cable assemblies ? high-speed printed circuit board (pcb) traces benefits ? thinner gauge cable ? extends cable reach 3x ?improved ber typical application circuit v dd cp losb in1[p,n] in2[p,n] in3[p,n] in4[p,n] out1[p,n] out2[p,n] out3[p,n] out4[p,n] dt 1.2v 10nf 100pf rx1[p,n] rx2[p,n] rx3[p,n] rx4[p,n] host asic active copper cable assembly 8-pair differential 100o twin-axial cable = 10m 28awg connector paddle card ISL36411 1.2v 100pf v dd de tdsbl in1[p,n] in2[p,n] in3[p,n] in4[p,n] out1[p,n] out2[p,n] out3[p,n] out4[p,n] 1.2v 10nf 100pf isl35411 tx4[p,n] tx3[p,n] tx2[p,n] tx1[p,n] host asic connector paddle card 0.1f 0.1f 0.1f 0.1f fabric switch host channel adapter 10nf 100pf 10nf 1.2v 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f dt caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved. all other trademarks mentioned are the property of their respective owners. march 25, 2010 fn6965.1
ISL36411 2 fn6965.1 march 25, 2010 pin configuration ISL36411 (46 ld qfn) top view ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL36411drz-ts ISL36411drz 0 to +85 46 ld qfn (7?? 100 pcs.) l46.4x7 ISL36411drz-t7 ISL36411drz 0 to +85 46 ld qfn (7? 1k pcs.) l46.4x7 notes: 1. ?-ts? and ?-t7? suffix is for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device in formation page for ISL36411 . for more information on msl please see techbrief tb363 . v dd in1[p] in1[n] losb1 v dd in2[p] in2[n] gnd nc dt1 cp1a cp1b gnd nc 1 2 3 4 5 6 7 46 45 44 43 42 41 40 8 9 10 11 12 13 14 15 39 16 17 18 19 20 21 22 23 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 losb2 v dd in3[p] in3[n] losb3 v dd in4[p] in4[n] out1[p] out1[n] v dd v dd out2[p] out2[n] v dd v dd out3[p] out3[n] v dd v dd out4[p] out4[n] v dd v dd exposed pad cp2b nc gnd dt2 losb4 cp2a nc gnd (gnd)
ISL36411 3 fn6965.1 march 25, 2010 pin functions and definitions pin name pin number description v dd 1, 5, 9, 13, 24, 27, 28, 31, 32, 35, 36, 39 power supply. 1.2v supply voltage. the use of para llel 100pf and 10nf decoupling capacitors to ground is recommended for each of these pins for broad high-frequency noise suppression. in1[p, n] 2, 3 equalizer 1 differential input, cml. th e use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. losb1 4 los bar indicator 1. low output wh en in1 signal is below dt threshold. in2[p, n] 6, 7 equalizer 2 differential input, cml. th e use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. losb2 8 los bar indicator 2. low output wh en in2 signal is below dt threshold. in3[p, n] 10, 11 equalizer 3 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. losb3 12 los bar indicator 3. low output when in3 signal is below dt threshold. in4[p, n] 14, 15 equalizer 4 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. losb4 16 los bar indicator 4. low output when in4 signal is below dt threshold. gnd 17, 23, 40, 46 these pins should be grounded. dt2 18 detection threshold for equalizers 3 and 4. reference dc voltage thre shold for input signal power detection. data output out3 and out4 are muted when the power of in3 and in4, respectively, fall below the threshold. tie to ground to disable electrical idle preservation and always enable the limiting amplifier. cp2[a,b] 19, 20 control pins for setting equalizers 3 and 4. cmos logic inputs . pins are read as a 2-digit number to set the boost level. a is the msb, and b is the lsb. pins are internally pulled down through a 25k resistor. nc 21, 22, 41, 45 not connected: do not make any connections to these pins. out4[n, p] 25, 26 equalizer 4 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. out3[n, p] 29, 30 equalizer 3 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. out2[n, p] 33, 34 equalizer 2 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. out1[n, p] 37, 38 equalizer 1 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. cp1[b, a] 42, 43 control pins for sett ing equalizers 1 and 2. cmos logic inpu ts. pins are read as a 2-digit number to set the boost level. a is the msb, and b is the lsb. pins are internally pulled down through a 25k resistor. dt1 44 detection threshold for equa lizers 1 and 2. reference dc vo ltage threshold for input signal power detection. data output out1 and out2 are muted when the power of in1 and in2, respectively, fall below the threshold. tie to ground to disable electrical idle preservation and always enable the limiting amplifier. exposed pad - exposed ground pad. for proper elec trical and thermal performance, this pad should be connected to the pcb ground plane.
ISL36411 4 fn6965.1 march 25, 2010 absolute maximum ratings thermal information supply voltage (v dd to gnd). . . . . . . . . . . . . -0.3v to 1.5v voltage at all input pins . . . . . . . . . . . . . . . . -0.3v to 1.5v esd ratings human body model high-speed pins . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kv all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv thermal resistance (typical) ja (c/w) jc (c/w) 46 ld qfn package (notes 4, 5) . . 33 2.8 operating ambient temperature range. . . . . . 0c to +85c storage ambient temperature range . . . . . -55c to +150c maximum junction temperature. . . . . . . . . . . . . . . +125c pb-free reflow profile. . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ja measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. operating conditions parameter symbol condition min typ max units supply voltage v dd 1.1 1.2 1.3 v operating ambient temperature t a 02585c bit rate nrz data applied to any channel 2.5 11.1 gbps control pin characteristics v dd = 1.2v, t a = +25c, and v in = 600mv p-p , unless otherwise noted. parameter symbol condition min typ max units output low logic level v ol los[k] 0 250 mv output high logic level v oh los[k] 750 v dd mv input current current draw on digital pin, i.e., cp[k][a,b] 100 200 a electrical specifications v dd = 1.2v, t a = +25c, and vin = 600mv p-p , unless otherwise noted. parameters symbol condition min typ max units notes supply current i dd 368 ma cable input amplitude range v in measured differentially at data source before encountering channel loss; up to 10m 28awg standard twin-axial cable (approx. -27db @ 5ghz) 600 1600 mv p-p 6 dc differential input resistance measured on input channel in[k] 80 100 120 dc single-ended input resistance measured on input channel in[k]p or in[k]n, with respect to v dd 40 50 60 input return loss limit (differential) s dd 11 100mhz to 4.1ghz note 7 db 7 4.1ghz to 11.1ghz note 8 db 8 input return loss limit (common mode) s cc 11 100mhz to 2.5ghz note 9 db 9 2.5ghz to 11.1ghz -3 db 14 input return loss limit (com. to diff. conversion) s dc 11 100mhz to 11.1ghz -10 db 14 output amplitude range v out measured differentia lly at out[k]p and out[k]n with 50 load on both output pins 450 600 850 mv p-p differential output impedance measured on out[k] 80 105 120
ISL36411 5 fn6965.1 march 25, 2010 output return loss limit (differential) s dd 22 100mhz to 4.1ghz note 7 db 7 4.1mhz to 11.1ghz note 8 db 8 output return loss limit (common mode) s cc 22 100mhz to 2.5ghz note 9 db 9 2.5mhz to 11.1ghz -3 db 14 output return loss limit (com. to diff. conversion) s dc 22 100mhz to 11.1ghz -10 db 14 output residual jitter 10gbps; up to 10m 28awg std twin- axial cable (~ -27db @ 5ghz); 1200mv p-p vin 1600mv p-p 0.35 ui 6, 10, 11 output transition time t r , t f 20% to 80% 32 ps 12 lane-to-lane skew 50 ps 14 propagation delay from in[k] to out[k] 500 ps 14 los assert time time to asse rt loss-of-signal indicator when transitioning from active data mode to line silence mode 50 s 13 los de-assert time time to assert loss-of-signal indicator when transitioning from line silence mode to active data mode 50 s 13 data-to-line silence response time k28.5 data pattern at 10gbps 100 s 13 data-to-line silence response time k28.5 data pattern at 10gbps 100 s 13 notes: 6. after channel loss, differential amplitudes at ISL36411 inpu ts must meet the input voltage range specified in ?absolute maximum ratings? on page 4. 7. maximum reflection coefficient give n by equation sddxx(db)= -12 + 2* (f), with f in ghz. esta blished by characterization and not production tested. 8. maximum reflection coefficient given by equation sddxx( db)= -6.3+13log10(f/5.5), with f in ghz. established by characterization and no t production tested. 9. reflection coeffici ent given by equation sccxx(db) < -7 + 1.6*f, with f in ghz. established by characterization and not production tested. 10. output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the tr ansmitted signal (as measured at the input to the channel). total jitter (tj) is dj pp + 14.1 x rj rms . 11. measured using a prbs 2 7 -1 pattern. deterministic jitter at the input to the lane extender is due to frequency-dependent, media-induced loss only. 12. rise and fall times measured using a 1ghz clock with a 20ps edge rate. 13. for active data mode, cable input amplitude is 300mv p-p (differential) or greater. for line silence mode, cabl e input amplitude is 20mv p-p (differential) or less. established by ch aracterization and no t production tested. 14. limits establishe d by characterization and ar e not production tested. electrical specifications v dd = 1.2v, t a = +25c, and vin = 600mv p-p , unless otherwise noted. (continued) parameters symbol condition min typ max units notes
ISL36411 6 fn6965.1 march 25, 2010 typical performance characteristics performance is measured using the test setup illustrated in fi gure 1. the signal from the pattern generator is launched into the twin-ax cable using an sma adapter card. the chip evaluation board is connected to the output of the cable through another adapter card. the ISL36411 output signal is then visualized on a scope to determine signal integrity parameters such as jitter. figure 1. device characterization set up figure 2. ISL36411 10.3125gb/s output for a 10m 28awg cable pattern generator sma adapter card 100o twin-axial cable sma adapter card ISL36411 eval board oscilloscope
ISL36411 7 fn6965.1 march 25, 2010 operation the ISL36411 is an advanced quad lane-extender for high-speed interconnects. a f unctional diagram of one of the four channels in the ISL36411 is shown in figure 3. in addition to a robust equalization filter to compensate for channel loss and restore signal fidelity, the ISL36411 contains unique integrated features to preserve special signaling protocols typically broken by other equalizers. the signal detect function is used to mute the channel output when the equalized si gnal falls below the level determined by the detection threshold (dt) pin voltage. this function is intended to preserve periods of line silence (?quiescent state? in infiniband contexts). furthermore, the output of the signal detect / dt comparator is used as a loss of signal (los) indicator to indicate the absence of a received signal. as illustrated in figure 3, the core of each high-speed signal path in the ISL36411 is a sophisticated equalizer followed by a limiting amplifier. the equalizer compensates for skin loss, dielectric loss, and impedance discontinuities in the transmission channel. each equalizer is followed by a limiting amplification stage that provides a clean output signal with full amplitude swing and fast rise-fall times for reliable signal decoding in a subsequent receiver. adjustable equalization boost each channel in the ISL36411 features a settable (in pairs) equalizer for custom signal restoration. the flexibility of this adjustable compensation architecture enables signal fidelity to be optimized on a channel-by-channel basis, providing support for a wide variety of channel characteristics and data rates ranging from 2.5gbps to 11.1gbps. because the boost level is externally set rather than internally adapted, the ISL36411 provides reliable communication from the very first bit transmitted. there is no time needed for adaptation and control loop convergence. furthermore, there are no pathological data pat-terns that will cause the ISL36411 to move to an incorrect boost level. control pin boost setting the connectivity of the cp pins is used to determine the boost level of each pair of channels. cp1 controls the boost of channels 1 and 2, cp2 controls the boosts of channels 3 and 4. table 1 defines the mapping from the 2-bit cp word to the 8 possible boost levels. figure 3. functional diagram of a single channel within the ISL36411 signal detector in[p] in[n] dt losb out[n] out[p] adjustable equalizer cpa cpb limiting amplifier output driver table 1. mapping between boost level and cp-pin connectivity cpa cpb boost level float float 0 float gnd 1 gnd vdd 2 float vdd 3 vdd float 4 gnd float 5 gnd gnd 6 vdd gnd 7 vdd vdd 8
ISL36411 8 fn6965.1 march 25, 2010 ISL36411 cml input an d output buffers the input and output buffers for the high-speed data channels in the ISL36411 are implemented using cml (shown in figures 4 and 5). line silence/quiescent mode line silence is commonly broken by the limiting amplification in other equalizers. this disruption can be detrimental in many systems that rely on line silence as part of the protocol. the ISL36411 contains special lane management capabilities to detect and preserve periods of line silence while still providing the fidelity-enhancing benefits of limiting amplification during active data transmission. line silence is detected by measuring the amplitude of the equalized signal and comparing that to a threshold set by the voltage at the dt pin. when the amplitude falls below the thre shold, the output driver stages are muted and held at their nominal common mode voltage 1 . los bar indicator pins losb[k] are used to output the state of the muting circuitry to serve as a loss of signal indicator for channel k. this signal is directly derived from the muting signal off the dt-threshold signal detector output. the los signal goes low when the power signal is below the dt threshold and high when the power goes above the dt threshold. this feature is meant to be used in optical systems (e.g. qsfp) where th ere are no quiescent or electrical-idle states. in these cases, the dt threshold is used to determine the sensitivity of the los indicator. detection thereshold (d t) pin functionality the ISL36411 is capable of maintaining periods of line silence by monitoring the channel for loss of signal (los) conditions and subsequently muting the output driver when such a condition is detected. a reference voltage applied to the detection threshold (dt) pins is used to set the los threshold of the internal signal detection circuitry (one pin for a pair of channels). the dt voltage is set with an external pull-up resistor, rdt. for typical applications, a 15k resistor is recommended for channels with loss greater than 12db at 5ghz, and a 0.9k resistor is recommended for lower loss channels. other values of the resistor may also be applicable; therefore dt settings should be verified on an application-specific basis. pcb layout considerations because of the high speed of the ISL36411 signals, careful pcb layout is critical to maximize performance. the following guidelines should be adhered to as closely as possible: ? all high speed differential pair traces should have a characteristic impedance of 50 with respect to ground plane and 100 with respect to each other. ? avoid using vias for high speed traces as this will create discontinuity in the traces? characteristic impedance. ? input and output traces need to have dc blocking capacitors (100nf). capacitors should be placed as close to the chip as possible. ? for each differential pair, the positive trace and the negative trace need to be of the same length in order to avoid intra-pair skew. a serpentine technique may be used to match trace lengths. ? maintain a constant solid ground plane underneath the high-speed differential traces. ? each vdd pin should be connected to 1.2v and also bypassed to ground through a 10nf and a 100pf capacitor in parallel. minimize the trace length and avoid vias between the vdd pin and the bypass capacitors in order to maximize the power supply noise rejection. ? if 4 channels of the device are set to the same boost, then the quantity of cp resistors can be reduced by tying both cp pins together. figure 4. cml input equivalent circuit figure 5. cml output equivalent circuit 1. the output common mode voltage remains constant duri ng both active data transmission and output muting modes in[p] in[n] 1 st filter stage v dd 50o 50o
ISL36411 9 fn6965.1 march 25, 2010 application information typical application schematic for ISL36411 is shown in figure 6. 1 2 3 4 5 6 7 8 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 16 17 18 19 20 21 22 2 3 9 10 11 12 13 14 15 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 cp3 [a] cp3[b ] cp1[a] c p1[b] 1.2v 1.2v 1.2v in1[p] in1[n] in2[p] in2[n] in3[p] in3[n] in4[p] in4[n] out2[p] out2[n] out4[p] out4[n] out1[p] out1[n] out3[p] out3[n] a ISL36411 1.2v 100pf* 10nf bypass circuit for each v dd pin (*100pf capacitor should be positioned closest to the pin) eq boost control for channels 1 and 2 losb4 gnd dt1 ISL36411 lane extender eq boost control for channels 3 and 4 a) dc blocking capacitors = x7r or cog 0.1f (>6ghz bandwidth) 1.2v dt2 nc 1.2v losb1 1.2v 1.2v losb2 1.2v losb3 nc gnd 1.2v gnd nc nc gnd 1.2v 1.2v 1.2v figure 6. typical application reference schematic for ISL36411 notes: 15. see ?control pin boost setting? on page 7 fo r information on how to connect the cp pins. 16. see ?detection thereshold (dt) pin functional ity? on page 8 for details on dt pin operation.
ISL36411 10 fn6965.1 march 25, 2010 about q:active? technology intersil has long realized that to enable the complex server clusters of next generation datacenters, it is critical to manage the signal integrity issues of electrical interconnects. to address this, intersil has developed its groundbreaking q:active? pr oduct line. by integrating its analog ics inside cabling interconnects, intersil is able to achieve unsurpassed improvements in reach, power consumption, latency, and cable gauge size as well as increased airflow in tomorrow?s datacenters. this new technology transforms passive cabling into intelligent ?roadways? that yield lower operating expenses and capital expenditures for the expanding datacenter. intersil lane extenders allow greater reach over existing cabling while reducing the need for thicker cables. this significantly reduces cable weight and clutter, increases airflow, and improves power consumption.
ISL36411 11 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6965.1 march 25, 2010 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: ISL36411 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 3/16/10 fn6965.1 page 4 ? control pin characteristics: vol : delete typical ?0? ? input current: max 200, typ 100 page 5 ? output res jitter: 0.35 ? in entries from lane-to-lane skew all the way down, all the numbers should move to typ column added high-speed pins to esd rati ngs as follows to abs max ratings: esd ratings human body model high-speed pins 1.5kv all other pins 2kv removed board footprint from page 10 due to information covered in outline drawing. 2/8/10 fn6965.0 initial release
ISL36411 12 fn6965.1 march 25, 2010 package outline drawing l46.4x7 46 lead thin quad flat no-lead plastic package (tqfn) rev 0, 9/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0.152 ref 0 . 05 max. 0 . 00 min. 5 4.00 a b 7.00 (4x) 0.05 6 pin 1 index area 39 46 2.80 42x 0.40 exp. dap 15 1 38 23 46x 0.40 16 6 5.60 ( 6.80 ) ( 5.50 ) ( 46 x 0.60) (46x 0.20) ( 42x 0.40) ( 3.80 ) ( 2.50) 2.50 0.1 0.10 46x 0.20 a mc b 4 5.50 0.1 exp. dap 0.70 0.05 see detail "x" seating plane 0.05 0.10 c c c 24 side view pin 1 index area

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